1. Field of the Invention
The present invention relates to the field of semiconductor devices and, in particular, to complementary metal oxide semiconductor (CMOS) image sensors.
2. Related Art
Thanks to the latest advances in technology, CMOS imagers have been used in various applications and have not been limited any more to consumer low-end applications only.
A typical CMOS imager comprises of a focal plane array of pixel cells, each one of the pixels further comprising a light detection component such as a photodiode, a photogate or a photoconductor. The pixel also has a readout circuit that is connected to its light detection node and may also include a sample-and-hold circuit for electronic shutter control either before or after the readout circuit. The CMOS imager pixel cell may include at least one transistor for transferring charge from the charge accumulation region of the substrate to the light detection node that can be a floating diffusion node and also has a transistor for resetting the light detection node to a predetermined charge level prior to charge transfer.
A widely-used Active Pixel Sensor (APS) is the 4-Transistor (4T) design which comprises of a photodiode that is typically reversed-biased, a sample-and-hold (SH) transistor which provides snap shot control connected to the light detection node, a reset transistor, a source-follower (SF) transistor which has a gate acting as signal storage for the sample-and-hold transistor SH and as the signal buffer amp, and a select transistor that connects the pixel to the column bus and allows the signal transfer from the pixel to the column amplifier. An APS is depicted in FIG. 1.
FIG. 1 depicts the widely used prior art Active Pixel Sensor of 4T (4 Transistors) design typically (but not always) realized with N-Type transistors. A CMOS imager comprises of array of pixels 100, one of which is shown here. The pixel 100 includes a reversed-biased photodiode 101 overlying a doped region of a substrate for accumulating photo-generated charge during the integration period. The photodiode 101 is reset to a predefined charge level prior to integration via a reset switch, such as a transistor 102 which is controlled by a reset clock signal 110 at its gate. A sample-and-hold transfer switch, such as a transistor 103, provides means of transferring the charge from the collection region and providing a corresponding voltage level on the gate of a source-follower transistor 104. A select transistor 105, which is controlled by a select clock 108 signal, outputs the signal corresponding to the photon-generated charge on to a column bus 107.
The reset transistor 102 resets the photodiode to a high level based on a process positive supply voltage VDD 106 that is connected to its drain and the reset clock 110 positive voltage that is usually limited to the fabrication process positive voltage VDD. Hence in this example, after the photodiode is reset to a level that is below VDD based on the threshold voltage, it will integrate down during the integration period. The voltage drifts with temperature changes, and thus the amount of loss in the dynamic range available for the photodiode integration drifts as well.
The source-follower 104 as explained previously receives on its gate the voltage level corresponding to the signal, while its drain is connected to VDD 106. Its threshold also drifts with temperature changes and thus the amount of loss in the dynamic range of the source-follower 104 also drifts.
It can be seen that for the pixel 100, the linear voltage range is limited to output voltage VOUT as follows:VOUT=VDD—Voltage threshold of reset transistor 102—Voltage threshold of source follower transistor 104—Saturation Voltage (drain-to-source voltage) of select transistor 105.For a typical 3.3V CMOS process, this range may be as low as 1 Volt.
The pixel 100 suffers from a condition known as “image lag”, where an incomplete charge transfer occurs through the sample-and-hold transistor 103 due to imperfect sampling of the signal. This results in non-linear operation of the sensor, especially at low signal levels, and increased noise.
The pixel 100 further suffers from reduced gain, because the integrated charge is divided between an integration node 111 and the gate of the source-follower transistor 104, thus reducing the sensitivity of the imager.
In addition, pixel 100 suffers from increased noise and non-linearity due to un-cleared output voltage of previous integration prior to transferring voltage representing the newly integrated charge (also referred to as “image ghost”). The result of the various losses described here is a drifting reduction in the total dynamic range of the output signal that can not be recovered off chip.
Furthermore, the pixel 100 suffers from decreased dynamic range due to clipping of the signal high range or the signal low range depending on the polarity of the photo-diode and the circuitry. The signal clipping is caused by the threshold voltage drop and temperature dependent drift of the various transistors.
Accordingly, it is desirable to have an active pixel sensor or circuit for use in CMOS imagers without the disadvantages of conventional circuits discussed above.